1. Field of the Invention
The present invention relates to a static random access memory (SRAM) having a thin film transistor (TFT) as a load transistor. In addition, the present invention relates to a semiconductor memory device having a gate insulator film, which is different from that formed in a memory portion, in a peripheral circuit portion.
2. Description of the Prior Art
In a semiconductor device such as an SRAM, a TFT is used as a load transistor to obtain a high integration level. In the SRAM, a driver transistor and a selector transistor are formed on the surface of a semiconductor substrate, and a thin film such as a semiconductor layer is formed on these transistors through an interlayer insulator, thereby forming a TFT serving as a load transistor. The TFT used as the load transistor of the SRAM has a bottom gate structure in which a gate electrode layer is formed on the lower layer side of a semiconductor layer through a gate insulator film.
In the steps in manufacturing the SRAM, since a portion of a polysilicon layer constituting the semiconductor layer must be connected to a specific gate electrode layer located on the lower layer side of the semiconductor layer, a contact hole is formed in the gate insulator film, and the polysilicon layer serving as the semiconductor layer is stacked on the gate insulator film by CVD or the like to be inserted in the contact hole. In this case, before the polysilicon layer serving as the semiconductor layer is formed by CVD, a native oxide formed on the surface of the gate electrode layer exposed in the contact hole must be removed by photo-etching.
However, the light etching causes the following problem. That is, a silicon oxide film constituting the gate insulator film is dipped in a photo-etching solution to degrade the quality of the gate insulator film.
When the thickness of the polysilicon layer constituting the semiconductor layer is decreased to suppress a leakage current from the TFT serving as the load transistor, since the polysilicon layer is also used as a power supply line connected to the TFT, the wiring resistance of the power supply line is increased, and the ON current of the TFT is disadvantageously decreased.
In addition, as the memory cell size of the SRAM is decreased, the capacitance of a storage node is decreased, and a resistance to soft errors is decreased.
A transistor having a breakdown voltage higher than that of each of memory cells may be formed at a portion of a peripheral circuit, arranged around a region having the memory cells, for driving the memory. In the high voltage transistor, since a high electric field is applied to a gate insulator film, the gate insulator film has a thickness larger than that of a transistor having a normal power supply voltage. However, even when the thickness of the gate insulator film of the high voltage transistor is different from that of a normal transistor, the high voltage transistor and the normal transistor have different subthreshold voltages. Therefore, an impurity is selectively ion-implanted in the semiconductor substrate to control both the transistors to have almost equal threshold voltages.
FIGS. 1A to 1F show a conventional method of manufacturing a semiconductor device having a P-channel high voltage transistor and a P-channel normal transistor. In this conventional method, as shown in FIG. 1A, wells 12 and 13 are formed in an Si substrate 11 as a region for forming the high voltage transistor and a region for forming the normal transistor, respectively. Although the wells 12 and 13 are of an N type, the well 12 has a concentration lower than that of the well 13.
Thereafter, a P.sup.- -type diffused layer 14 is formed in the well 12 to extend a depletion layer formed by a drain voltage in the high voltage transistor. Local oxidation is performed to the resultant structure to form an SiO.sub.2 film 15 serving as a field oxide, and gate oxidation is performed to the resultant structure to form an SiO.sub.2 film 16 having a thickness of about 200 .ANG. as shown in FIG. 1B.
As shown in FIG. 1C, a resist 17 is patterned to cover only a region of the SiO.sub.2 film 16 on which the gate oxide of the high voltage transistor is to be formed. The resultant structure is etched using the resist 17 as a mask to selectively remove the SiO.sub.2 film 16.
After the resist 17 is removed, gate oxidation is performed to the resultant structure again, and as shown in FIG. 1D, an SiO.sub.2 film 21 having a thickness of about 200 .ANG. is formed in a region from which the SiO.sub.2 film 16 is removed. At the same time, an SiO.sub.2 film 22 having a thickness of about 300 .ANG. is formed by the remaining SiO.sub.2 film 16.
As shown in FIG. 1E, a resist 23 is patterned to cover only a region prospectively serving as the channel region of the high voltage transistor. Boron 24 is ion-implanted in the Si substrate 11 using the resist 23 and the SiO.sub.2 film 15 as masks to control the threshold voltage of the normal transistor to be formed in the well 13.
In the high voltage transistor, the impurity concentration of the well 12 is determined at the beginning such that a desired threshold voltage is obtained with respect to the thickness of the SiO.sub.2 film 22 without ion implantation of the boron 24. In contrast to this, the threshold voltage of the normal transistor to be formed in the well 13 and the threshold voltage of an N-channel transistor (not shown) are simultaneously controlled by the ion implantation of the boron 24. For this reason, since the impurity concentration of the well 13 is excessively high with respect to the thickness of the SiO.sub.2 film 21 to obtain a desired threshold voltage, the boron 24 is ion-implanted in the well 13.
As shown in FIG. 1F, after the resist 23 is removed, a poly-Si film 25 is deposited on the entire surface of the resultant structure by CVD, an impurity is doped in the poly-Si film 25, and the poly-Si film 25 is patterned to form gate electrodes. Sidewalls constituted by SiO.sub.2 films 26 are formed on the side surfaces of the poly-Si films 25.
Boron or the like is ion-implanted in the resultant structure using the poly-Si films 25 and the SiO.sub.2 films 15 and 26 as masks to form P.sup.+ -type diffused layers 27 serving as the source/drain regions of the transistors in the wells 12 and 13. Thereafter, an A1 electrode wiring or the like are formed in the conventionally known steps. In this manner, a high voltage transistor 31 and a normal transistor 32 are formed in the wells 12 and 13, respectively.
However, in the prior art shown in FIGS. 1A to 1F, as is apparent from the steps in FIGS. 1C to 1E, when the SiO film 16 is to be etched to cause the thicknesses of the gate oxides of both the transistors to be different from each other, and the boron 24 is to be ion-implanted to control the threshold voltage of the normal transistor, the different resists 17 and 23 are used as masks. For this reason, the number of steps of forming and removing the masks is large, and the number of additional steps required for forming the high voltage transistor 31 and the normal transistor 32 on the same chip is increased, thereby increasing production cost.